1. Field
This disclosure relates generally to an integrated circuit and, more specifically, to techniques for providing switchable decoupling capacitors for an integrated circuit.
2. Related Art
As voltage domains (associated with logic islands (blocks)) of an integrated circuit (chip) become active with workloads, the logic islands can deplete an available local charge provided by an associated decoupling capacitor. Moreover, as chip designers migrate chip designs to more complex chip designs (e.g., single core processor designs to multi-core processor designs), a power delivery aspect of a chip design has usually become increasingly more complex. For example, in a multi-core processor design, each of the processor cores may be associated with a separate voltage domain that is managed to reduce power consumption (e.g., one or more of the cores may be powered-down during periods of inactivity while remaining ones of the cores are powered-up).
U.S. Patent Application Publication No. 2007/0138653 (hereinafter the '653 application) is directed to a power control structure for managing (to reduce leakage current and overall power dissipation) a plurality of voltage domains (each associated with a different logic island) of a functional chip. The '653 application discloses the use of a silicon carrier that supplies decoupling capacitors for the voltage domains and includes control circuitry for selectively supplying power to the voltage domains of the chip. As is disclosed, when a voltage domain is disabled, the voltage domain may be powered down to reduce overall chip power dissipation.
With reference to FIG. 1, a relevant portion of a conventional power distribution system 100 is illustrated that selectively provides power and decoupling capacitance to power supply terminals (VDD1 and VDD2) of logic islands (labeled ‘Logic Island 1’ and ‘Logic Island 2’, respectively) 104 and 106 of a functional chip 102. As is illustrated, a silicon carrier 120 includes p-channel field-effect transistors (PFETS) 106 and 108, decoupling capacitors C1 and C2, and n-channel field-effect transistors (NFETS) 110 and 112. A control circuit (not shown) provides a first control signal (CCNTL_1) to a gate of the PFET 106 and a second control signal (CCNTL_2) to a gate of the PFET 108. The first control signal, when asserted, couples the capacitor C1 to the terminal VDD1 of the logic island 104 and the second control signal, when asserted, couples the capacitor C2 to the terminal VDD2 of the logic island 106. The NFETs 110 and 112 couple a shared power supply VDD to the VDD1 and VDD2 terminals of the chip 102 responsive to control signals VCNTL_1 and VCNTL_2 (which are also provided by the control circuit), respectively. It should be noted that the capacitor C1 is dedicated to the logic island 104 and the capacitor C2 is dedicated to the logic island 106.
U.S. Pat. No. 6,967,416 (hereinafter the '416 patent) discloses selectively connecting/disconnecting decoupling capacitors (to/from a power supply terminal), such that inactive decoupling capacitors provide a uniform heat dissipation function across a chip and active decoupling capacitors provide a uniform power regulation function across the chip. According to the '416 patent, capacitors within a group are either ‘enabled’ to provide charge storage for an associated voltage domain, or ‘disabled’ from providing charge storage for the associated voltage domain (in which case the disabled capacitors function as heat sinks).
While on-die capacitance may be incorporated within a functional chip to increase local charge, incorporating on-die capacitance within a high performance functional chip is relatively expensive and may increase a chip failure rate. Moreover, while discrete decoupling capacitors may be incorporated at various packaging levels (in an attempt to improve filtering), employing discrete decoupling capacitors may create undesirable inductive loops in a power distribution system and may not provide adequate local charge.